Celero Communications has raised $275 million in Series C funding following validation of its first 2nm coherent DSP silicon, giving the two-year-old semiconductor company substantial new capital to pursue the rapidly expanding optical interconnect opportunity around AI infrastructure. The financing brings Celero's total funding to $415 million and values the company at more than $3 billion. Atreides Management, Valor Equity Partners and CapitalG led the round, with participation from existing investors including Sutter Hill Ventures and Maverick Silicon. Atreides Managing Partner and CIO Gavin Baker will join Celero's board. The announcement matters because it brings another advanced-node coherent DSP supplier into a market where AI is expanding the addressable role of coherent optics beyond its established footprint.
The more significant technical milestone is Celero's validation of a 2nm coherent DSP incorporating both digital signal processing and advanced analog technology. Celero says the architecture provides a scalable path from 1.6T optical connectivity to next-generation 3.2T AI optical interconnects, with the advanced process node aimed at reducing power while increasing bandwidth density and fiber efficiency. The company is positioning coherent technology beyond its established role in metro and data center interconnect, targeting the growing connectivity requirements associated with Scale Up, Scale Out and Scale Across AI architectures. The new capital will support R&D;, expansion of the product roadmap and production readiness. Founded in 2024, Celero brings together a veteran coherent-DSP team with backgrounds at Marvell, Inphi, Broadcom and ClariPhy. CEO and co-founder Nariman Yousefi previously led businesses spanning switching and coherent DSP at Inphi and Marvell and earlier served at Broadcom and as CEO of ClariPhy; CTO and co-founder Oscar Agazzi was previously CTO and SVP at ClariPhy, Inphi and Marvell. The company is headquartered in Irvine, California, with design centers in Canada and Argentina.
The evidence for this development comes from a single Converge Digest report read in full. The source quotes Yousefi directly: "AI infrastructure is rapidly outgrowing the capabilities of traditional optical interconnect architectures. Our 2nm silicon validation demonstrates that coherent technology can deliver the bandwidth density, power efficiency and scalability required for the next generation of AI networks." The report also provides competitive context, noting that in March Marvell introduced its Electra 2nm coherent DSP for 1.6T ZR/ZR+ and its Libra 2nm DSP for 800G ZR/ZR+. Marvell's roadmap emphasizes Scale Across connectivity between AI data centers, while Celero is describing a broader architecture extending from 1.6T toward 3.2T and spanning Scale Up, Scale Out and Scale Across. Celero has not yet disclosed the detailed reach, modulation, power, module architecture or production schedule needed to compare its implementation directly with shipping or sampling products from established coherent suppliers.
The sector implications are substantial. Historically, coherent DSPs have been optimized primarily for telecom transport, metro networks and increasingly ZR/ZR+ data center interconnect. AI infrastructure is now pushing the technology toward shorter reaches as operators confront higher lane rates, fiber-density constraints and power limits. The 3.2T target is particularly important: the optical ecosystem is already developing 400G-per-lane components and photonic devices capable of supporting 3.2T modules, while industry discussions increasingly place coherent technology alongside IMDD, CPO and other architectures as optical connectivity moves closer to AI compute. Celero is entering a market in which established suppliers are already moving coherent DSPs to advanced process nodes, but its $415 million capital base and validated 2nm silicon give it significant resources to move toward production.
The key limitation is that validation of 2nm silicon establishes only that the architecture has reached physical silicon. The substantially harder transition from silicon validation to commercial deployment remains ahead. For Celero, the next important milestones will be product specifications, customer sampling and production readiness. The source does not provide corroborating documentation from Celero, investor statements beyond the board appointment, or independent technical verification of the validation claim. Investors and competitors will be watching whether Celero can convert a validated 2nm DSP and a $275 million capital infusion into sampling timelines and customer engagements that compete with established coherent suppliers already moving to advanced nodes.